1. Technical Field
This disclosure is related to the manufacture of semiconductor devices, and in particular, the manufacture of fan-out wafer level packaging of semiconductor dies.
2. Description of the Related Art
Fan-out wafer-level packaging is a packaging process in which contacts of a semiconductor die are redistributed over a larger area. FIG. 1 shows a cross sectional diagram of a package-on-package (PoP) assembly 100 that includes a fan-out wafer level package (FOWLP) 102 and a plurality of additional semiconductor devices 104 coupled thereto.
The FOWLP includes a semiconductor die 106 embedded in a molding compound layer (MCL) 108, with a first redistribution layer 110 positioned on a first face 111 of the MCL and a second redistribution layer 113 positioned on the opposing second face 115. The first redistribution layer 110 comprises a plurality of electrical traces 112 and vias 114 separated by dielectric material 116, which place contact pads 118 of the die 106 in electrical contact with contact pads 120 of the package 102. Additionally, through-wafer vias (TWV) 122 in the MCL 108 place various of the plurality of electrical traces 112 in electrical contact with corresponding elements of the second redistribution layer 113. A first ball grid array (BGA) comprises a plurality of solder balls 126 positioned on respective ones of the contact pads 120, which, during a reflow process, will serve to electrically and mechanically couple the package 102 to a printed circuit board.
In the example of FIG. 1, the plurality of additional semiconductor devices 104 includes devices 128 in which through-silicon vias (TSV) 130 are provided according to known processes. Each of the additional semiconductor devices 104 is provided with a respective BGA 136 to couple contact pads 132 of that device to contact pads 134 of the device on which it is positioned.
Configurations like the PoP assembly 100 of FIG. 1 provide a number of advantages over traditionally packaged devices, including reduced manufacturing costs and reduced size. Such packaging is particularly beneficial in very small and complex electronic devices, including, for example, cell phones and “smart” phones.
Referring again to the FOWLP 102 of FIG. 1, in manufacturing these devices, a number of processes are known for use in providing the TWVs 122 in the MCL 108. According to one method, conductive bumps are printed onto a carrier substrate on which the semiconductor material die 106 is later positioned, and both are then embedded in molding compound. This process is described in detail in U.S. Pat. No. 6,714,418.
According to another method, TWVs are formed using techniques similar to those commonly used to form plated through-holes in printed circuit boards, as described, for example, in U.S. Pat. No. 7,598,607.
Dry film resist is a photosensitive film that is most commonly used in the manufacture of printed circuit boards as a plating mold in the process of depositing copper wiring patterns. Dry film resist is available in a wide range of thicknesses and formulations, typically consisting of three layers: a polyester support layer, a resist layer, and a polyethylene cover layer.
In use, the polyethylene cover layer is first removed, then the film is positioned with the resist side against a substrate, e.g., a resin substrate for a circuit board, under even pressure and a temperature of around 100 degrees C., to cause the resist layer to adhere to the surface of the substrate. The film is commonly applied using a roller or a vacuum press to apply the pressure. A mask is then positioned over the (transparent) polyester support layer of the film and the film is exposed to a light source. In the case of a positive-acting film, the portions of the film that are exposed to the light will dissolve and wash away during a subsequent developing process, and in the case of a negative acting film, the non-exposed portions will be removed during developing. After exposure to the light, the mask is removed, and the polyester support layer is peeled away, leaving the resist layer on the surface of the substrate. The resist layer is developed, by a process that varies according to the variety of film used, to remove the portion of the resist layer that is not desired, leaving the patterned layer behind. Where the dry film resist is used as a plating resist, a seed layer is typically deposited on the substrate prior to deposition of the film. After the film layer is patterned, the substrate is electroplated with copper, which adheres to the substrate at the locations where removal of the resist layer has exposed the seed layer. following the plating step, the resist layer is removed, leaving a copper circuit pattern formed on the substrate of the circuit board. Lastly, a short etch step removes a thickness of copper slightly in excess of the thickness of the seed layer, which is thereby removed from the substrate.
Dry film resist is also occasionally used as an etch resist when circuit boards are made by a subtractive process, and has also been investigated experimentally for use as a plating mold in the manufacture of MEMS devices. Dry film resist is commonly available in thicknesses (of the resist layer) ranging from around 15 to 75 μm (microns), with thicknesses up to around 200 μm being used in the MEMS investigations.
Electrically conductive paste is a polymeric material that includes a conductive ingredient. It is sometimes used in the manufacture of printed circuit boards (PCB) to fill through-holes and blind vias. Conductive paste is typically applied via screen printing, metal foil stencil, roller coating, or with a doctor blade. A vacuum assist is often used to draw the paste through the holes. In this manner, holes having high aspect ratios can be filled. Where conductive paste is used to fill blind vias, the aspect ratio of the holes must be low, generally less than 1:1, to permit the paste to fill the holes without trapping significant quantities of air. Deposition of conductive paste typically leaves a bump or blob of paste on one or both faces of a board or layer, so except where such a bump will not interfere with subsequent assembly steps, circuit boards or lamina are either wiped clean, if that can be done prior to curing the paste, or they are planarized or polished after curing.